Oct 14, 2013

VLSI Concepts: Maximum Clock Frequency : Static Timing Analysis (...

VLSI Concepts: Maximum Clock Frequency : Static Timing Analysis (...: Part1 Part2 Part3a Part3b Part3c Part4a Part4b Part4c Part5a Part5b   Part6a Part6b Part6c Stat...
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Oct 11, 2013

EE685: VLSI Broadband Communication Circuits, Aug-Nov 2007



http://www.ee.iitm.ac.in/~nagendra/videolectures/doku.php?id=ee685:start
These lectures are available on the web for the benefit of students at IIT Madras and elsewhere. Copyrights to these rest solely with the instructor and IIT Madras. Copying them, publishing them, rehosting them on other servers, or using them for any sort of commercial gain is prohibited.

Instructor: Nagendra Krishnapura

Course syllabus, schedule, and assignments can be seen here. Thanks are due to TAs-Vikas, Shankar, and Prashanth-for editing and producing the videos. If you wish to download these lectures for offline viewing, save the .swf file and view it in a browser with flash plugin or a standalone flash player. The pdf files contain the journal snapshots.
You can download the entire set of lectures(526MB). The archive contains directories for each day's lecture. It also has an index file 2007-ee685-nkrishnapura.html from which you can access the lectures.
  1. 2007-07-30 (pdf): Introduction to broadband digital communication
  2. 2007-07-31 (pdf): Introduction to broadband digital communication
  3. 2007-08-03 (pdf): Serializers and deserializers
  4. 2007-08-06(pdf): Power and delay in CMOS and current driven logic circuits (Forgot to hit “record”!)
  5. 2007-08-07 (pdf): CMOS logic, single ended data transmission, limitations
  6. 2007-08-08 (pdf): Current mode logic-basic circuit design
  7. 2007-08-10 (pdf): Current mode logic-MUX, XOR, latch
  8. 2007-08-13 (pdf): Current mode logic-latch design
  9. 2007-08-14 (pdf): Current mode logic-latch characteristics
  10. 2007-08-17 (pdf): Low pass transmission channel-Intersymbol interference, error rate
  11. 2007-08-20 (pdf): First order channel model, ISI
  12. 2007-08-21 (pdf): ISI, jitter, eye opening
  13. 2007-08-22 (pdf): Channel characteristics-Intersymbol interference, Crosstalk
  14. 2007-08-24 (pdf): Equalizer design
  15. 2007-08-28 (pdf): Equalizer design-minimizing the residual error
  16. 2007-08-31 (pdf): Equalization-Effect on noise and crosstalk
  17. 2007-09-03 (pdf): Tradeoffs between equalization at Tx and Rx; Design of Tx equalizers
  18. 2007-09-04 (pdf): Design of Transmit equalizers using flip-flops and transconductors
  19. 2007-09-05 (pdf): Tx equalizer-design considerations
  20. 2007-09-07 (pdf): Tx equalizer-design considerations; realizing variable coefficients
  21. 2007-09-10 (pdf): Differential pair-effect of tail node capacitance; Continuous time equalization
  22. 2007-09-11 (pdf): Continuous-time equalizer realization; replica biasing for the tail current source
  23. 2007-09-12 (pdf): Assignment 2 discussion
  24. 2007-09-14 (pdf): Replica biasing, optimizing transmitter swing
  25. 2007-09-17 (pdf): Replica biasing, optimizing transmitter swing
  26. 2007-09-18 (pdf): Analog layout optimization; Equalization at the receiver
  27. 2007-09-19 (pdf): Equalization at the receiver; Basics of adaptation
  28. 2007-09-24 (pdf): LMS adaptation
  29. 2007-09-25 (pdf): Sign-sign LMS adaptation
  30. 2007-09-26 (pdf): LMS implementation details
  31. 2007-09-28 (pdf): Adaptive equalizer implementation, S/H based equalizer, obtaining the gradients
  32. 2007-10-01 (pdf): Mid term discussion; Multiplexed and demultiplexed PRBS sequences; Latch vs. amplifier; Zeros for pre- and post- cursor equalization; Echo cancellation
  33. 2007-10-03 (pdf): Decision feedback equalizers-elimination of noise enhancement; Error propagation
  34. 2007-10-08 (pdf): Decision feedback equalizers-bit error rate
  35. 2007-10-09 (pdf): Decision feedback equalizers-implementation issues
  36. 2007-10-10 (pdf): Assignment 3 discussion
  37. 2007-10-12 (pdf): Decision feedback equalizers-implementation issues
  38. 2007-10-13 (pdf): Introduction to clock and data recovery-Frequency multiplication using a phase locked loop
  39. 2007-10-13 (pdf): Type I PLL; derivation of the phase model of the PLL; Tri state phase detector
  40. 2007-10-13 (pdf): (continued) Type I PLL; derivation of the phase model of the PLL; Tri state phase detector
  41. 2007-10-15 (pdf): Type I PLL; Reference feedthrough; Tradeoff between reference feedthrough and lock range
  42. 2007-10-16 (pdf): Stability of feedback loops; Derivation of the type II PLL
  43. 2007-10-26 (pdf): Realization of type II PLLs-charge pump, loop filter
  44. 2007-10-29 (pdf): Reference feedthrough in a type II PLL; Phase detector for random data
  45. 2007-10-30 (pdf): Linear phase detector for random data
  46. 2007-10-31 (pdf): Linear phase detector; Transfer functions in a PLL
  47. 2007-11-02 (pdf): PLL review
  48. 2007-11-05 (pdf): Binary phase detectors; bang bang jitter
  49. 2007-11-16 (pdf): Miscellaneous topics-Optimal equalizers; Linearity assumption of PLL model; PLL capture phenomenon; Hogge phase detector offset correction
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Oct 10, 2013

ECEN 720: High-Speed Links Circuits and Systems






    ECEN 720: High-Speed Links Circuits and Systems

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Dennis Fischette's 1-Stop PLL Center

Dennis Fischette's 1-Stop PLL Center

 http://www.delroy.com/PLL_dir/pll.htm

IEEE Distinguished Lecturer Series PLL Tutorial
Abstract
2009 Tutorial (Adobe PDF version (4.4MB) )
2007 Tutorial (Adobe PDF version (3.5MB) )

2004 ISSCC PLL Tutorial
Abstract
Microsoft Powerpoint version (861KB)
Adobe PDF version (484KB)

ISSCC 2010 Paper 13.2: A 45nm SOI Dual-PLL Processor Clock System for Multi-Protocol I/O
Presentation Slides (Adobe PDF version (1.6MB)

CICC 2009 Paper 19.3: An On-Chip, All-Digital Measurement Circuit to Characterize PLL Loop Response in 45n SOI
Paper (Adobe PDF version (0.6MB)
Presentation Slides (Adobe PDF version (1.8MB) )

Frequently Asked PLL Questions

PLL Behavioral Simulation and Analysis
PLLUS - under construction



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