- ECEN 720: High-Speed Links Circuits and Systems
Prof. Palermo's Office Hours
MW 2:00PM-3:30PM, WERC 315E
TA Noah Yang's Office Hours
Th 1:00PM-3:00PM, WERC 105
M 5:45PM-7:35PM, ZACH 203 (Lab) or WERC 105Class Notes
Lecture 1 - Introduction
Lecture 2 - Channel Components, Wires, & Transmission Lines
Lecture 3 - TDR & S-Parameter Channel Models
Lecture 4 - Channel Pulse Model & Modulation Schemes
Lecture 5 - Termination, TX Driver, and Multiplexer Circuits
Lecture 6 - RX Circuits
Lecture 7 - Equalization Intro & TX FIR EQ
Lecture 8 - RX FIR, CTLE, & DFE Equalization
Lecture 9 - Noise Sources
Lecture 10 - Jitter
Lecture 11 - Clocking Architectures & PLLs
Lecture 12 - CDRs
Lecture 13 - Forwarded Clock Deskew Circuits
Lecture 14 - Clock Distribution Techniques
2012 Notes
Lecture 21 - Optical I/O
Reading
1/14/2013
Electrical Links - Palermo - 2011
Electrical Links - Horowitz - 1998
Backplane Link - Bulzacchelli - 2006
Low-Power Source-Synchronous Link - Balamurugan - 2008
ADC-Based Link - Harwood - 2008
Optical Link - Palermo - 2008
1/24/2013
TDR Theory - Agilent
S-Parameter Tutorial - Agilent
S-Parameter Application Note - Agilent
2/5/2013
Peak Distortion and Statistical ISI Analysis Paper
PAM2/4 Transceiver - RAMBUS
Duobinary Transceiver - NEC Presentation
Duobinary Signaling - Bell Labs
NRZ/PAM-4/Duobinary Transceivers - NTU
Voltage-Mode TX Papers
XCVR w/ Low-Swing Voltage-Mode Driver - UCLA
XCVR w/ Low-Swing Voltage-Mode Driver - RAMBUS
High-Swing Voltage-Mode Driver - IBM
High-Swing Voltage-Mode Driver - Hitachi
High-Speed TX Mux Papers
XCVR w/ Output Multiplexing Driver - Stanford
XCVR w/ Input Multiplexing - Stanford
2/18/2013
Sampler Analysis - Linkoping
Optimized Strong-Arm Flip-Flop - UC-Davis
Comparator Analysis - Stanford
Comparator Characterization - RAMBUS
Comparator Metastability Analysis - Designer's Guide
PAM4 XCVR w/ Comparator Comparison - IBM
Low Voltage Comparator - Schinkel
Low Voltage Comparator - Goll
3/5/2013
HS Link Equalization Overview - Oregon St.
RX FIR
T/2 RX FIR - Broadcom
RX CTLE
RX CTLE - UCLA
RX DFE
Direct Feedback DFE - TI
Integrating DFE - IBM
DFE w/ IIR Filter - IBM Presentation
Other Approaches
Advanced Signaling - Rambus
3/27/2013
Stateye Theory
Jitter & BER - Agilent
Dual-Dirac Jitter Model - Agilent
High-Speed Link Clocking Tutorial - Intel
PLL Jitter Optimization - UCLA
PLL Thesis - UCLA
4/10/2013
CDR Comparisons - UMinn
CDR Challenges - UCLA
Digital CDR Thesis - Stanford (Ch 2 & 4)
Digital CDR Analysis - Synopsis
Injection-Locked LC Osc. De-Skew - Intel
Forwarded Clock ILO Deskew - UToronto
Sub-Harmonic ILO - UToronto
Forwarded Clock Bandpass Filtering - BYU
RX Jitter Tracking in Fwd Clk Systems - TAMU
2012 Reading
4/20/2011
Serial Link Clock Distribution - Oregon St.
Lab
M 5:45PM-7:35PM, ZACH 203
Lab 1 90nm CMOS Cadence Setup Solution
Lab 2 12" Backplane S-Parameter Data read_sparam.mxfr_fn_to_imp.m channel_data.m Solution
Lab 3 Solution
Lab 4 Prelab 4 Solution
Lab 5 TX FIR w/ PDA Matlab Code TX FIR Eq Function
TX FIR Cadence Example
CTLE Equalization Example CTLE Function
DFE Equalization Example
Lab 6
Homework
Homework 1
Exams
Exam 1
Sample Exam1 #1 Sample Exam1 #2 Sample Exam1 #3
Exam1 Solution Exam1 Statistics
Exam 2
Sample Exam2 #1 Sample Exam2 #2 Sample Exam2 #3
Exam2 Solution Exam2 Statistics
Project
Project Description
B1 Channel B1-FEXT1 B1-FEXT2 B1-NEXT1 B1-NEXT2
C4 Channel C4-FEXT C4-NEXT1 C4-NEXT2
T20 Channel T20-FEXT1 T20-FEXT2 T20-NEXT1 T20-NEXT2
T20 Channel Transient Simulation Issues
Key Project References
TX-IIR Equalizer - Netlogic
DFE-IIR Equalizer - NTU
DFE & FEXT Cancellation - CalTech
PLL Model & PRBS Documentation PLL Frequency Domain ModelPLL Time Domain Model (Simulink)
Additional Links
Published Electrical Serial Link Data
Dennis Fischette's PLL Tutorial Page
WPI Analog Lab - Excellent Jitter Notes
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